Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems
Type
conferenceObject
Publisher
Identifier
FONSECA, J.A.; MARTINS, E.V.; NEVES, P. - Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems. In IEEE International Conference on Electronics, Circuits and Systems, 8, Malta, 2 a 5 de Setembro de 2001. ICECS 2001. [S.l] : IEEE, 2001. ISBN 0-7803-7057-0. Vol.3, p.1485-1490
0-7803-7057-0
Title
Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems
Subject
Hardware co-processor
FPGA - Fiel Programmable Gate Arrays
Controller area network
Message scheduling in fieldbus systems
Fieldbus
FPGA - Fiel Programmable Gate Arrays
Controller area network
Message scheduling in fieldbus systems
Fieldbus
Date
2011-01-27T16:02:13Z
2011-01-27T16:02:13Z
2001-09-02
2011-01-27T16:02:13Z
2001-09-02
Description
“Copyright © [2001] IEEE. Reprinted from 8th IEEE International Conference on Electronics, Circuits and Systems. ISBN:0-7803-7057-0. This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.”
Fieldbus based distributed embedded systems used in real-time applications tend to be inflexible in what concerns changing operational parameters on-line. Recent techniques such as the planning scheduler can avoid this problem but do not show adequate responsiveness f o r automatic negotiation of parameter values. In this paper the use of ASIC based coprocessors f o r message scheduling is proposed to solve the problem. Such coprocessors can be used in the arbiter nodes of systems based on widely used producer-consumer fieldbuses like WorldFIP and CAN. A prototype built with a Xilinx FPGA is presented. First performance results are shown and analyzed. They demonstrate that the device is able to achieve the expected performance and also point to the possibility of evolution to an almost dynamic scheduling approach.
Fieldbus based distributed embedded systems used in real-time applications tend to be inflexible in what concerns changing operational parameters on-line. Recent techniques such as the planning scheduler can avoid this problem but do not show adequate responsiveness f o r automatic negotiation of parameter values. In this paper the use of ASIC based coprocessors f o r message scheduling is proposed to solve the problem. Such coprocessors can be used in the arbiter nodes of systems based on widely used producer-consumer fieldbuses like WorldFIP and CAN. A prototype built with a Xilinx FPGA is presented. First performance results are shown and analyzed. They demonstrate that the device is able to achieve the expected performance and also point to the possibility of evolution to an almost dynamic scheduling approach.
Access restrictions
openAccess
Language
eng
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