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The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational ̄exibility and timeliness guarantees. It is particularly well adapted to embedded systems based on low-processing power microcontrollers due to the low overhead it imposes. In this paper a preliminary implementation of a hardware scheduling coprocessor based on the planning paradigm is presented. The coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU. With this solution it is possible to decrease the response time to changes in the system con®guration or message parameters of the software- based planning scheduler. This opens the possibility of allowing automatic on-line changes requested by system nodes in addition to the ones requested by human operators, thus improving system reactivity. The paper includes a short review of the planning technique and a discussion on the motivation to develop the coprocessor as well as on recent similar and related work. The coprocessor architecture and several implementation details such as its interface with the arbiter CPU are presented. The initial calculations showing the feasibility of the unit are also derived, together with the first real implementation of the coprocessor itself.
“Copyright © [2001] IEEE. Reprinted from 8th IEEE International Conference on Electronics, Circuits and Systems. ISBN:0-7803-7057-0. This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.”
This paper considers approaches to the design and implementation of embedded systems using XC6200 FPGAs. The methods that are introduced enable the synthesis of circuits that are modifiable and extensible, and that provide a virtual function capability. The accepted behavioral specification supports modularity and hierarchy. The developed design tools allow translating this specification into dynamically modifiable control circuits. A method based on reconfigurable cores for rapid design of reconfigurable virtual datapath was suggested. A stand-alone board using one XC6216 FPGA was designed and two other solutions, currently under development, were discussed. They can be used as virtual embedded controllers. An integrated design environment (IDELS) has been developed to provide specification, synthesis, simulation, testing, debugging, and implementation of the circuits in hardware. The software has been developed using Visual C++ and allows access to both stand-alone and built-in PC boards.